2024-170 - Deterministic Benchmarking: fast and scalable calibration of qubit logic gates to minimize downtime

Description:

 

Background

To enable fault-tolerant quantum computing and reliable quantum simulations for drug development and materials science, quantum hardware must move beyond "noisy" prototypes to commercial-grade stability. Current benchmarking standards often miss systematic coherent errors that accumulate quadratically, creating a hidden bottleneck for scalability. With the right protocol, hardware providers can slash experimental overhead while identifying the specific noise profiles required for large-scale fault tolerance. This is the essential quality-control infrastructure needed to turn quantum chips into reliable, high-performance tools for the most demanding enterprise applications.

USC Solution

USC researchers have developed Deterministic Benchmarking (DB), an advanced protocol for characterizing single-qubit gates that bridges the gap between the speed of Randomized Benchmarking (RB) and the granular detail of Quantum Process Tomography (QPT). It is specifically designed to provide high-fidelity error maps without the massive experimental overhead of traditional tomography. This novel protocol minimizes number of experimental runs, exhibits resilience to State Preparation and Measurement (SPAM) errors, and effectively characterizes both coherent and incoherent errors. Unlike standard benchmarking, which relies on long sequences of random gates to "average out" noise, DB uses a fixed, minimal set of pulse-pair sequences. DB is the ideal 'goldilocks' solution for the next generation of quantum processors: maximum diagnostic insight with minimum experimental downtime.

Benefits

  • Coherent and incoherent error detection
  • State Preparation and Measurement (SPAM) resilience
  • Speed & scalability
  • No randomization required

Key References

Tripathi, V., Kowsari, D., Saurav, K., Zhang, H., Levenson-Falk, E.M. and Lidar, D.A., 2025. Benchmarking quantum gates and circuits. Chemical Reviews. https://doi.org/10.1021/acs.chemrev.4c00870

Patent Information:

  • Title: Simple and Accurate Calibration of Qubit Logic Gates
  • App Type: Utility
  • Country: United States
  • Serial No.: 19/722,211
  • Patent No.:  
  • File Date: 6/26/2026
  • Issued Date:  
  • Expire Date:  
  • Patent Status: Patent Pending