Search Results - mike+shuo-wei+chen

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2019-130 - Sub-Harmonic Switching Power Amplifier

Market Opportunity Modern radiofrequency (RF) communication systems have high spectral efficiency modulations, which lead to large peak to average power ratios (PAPRs). To prevent excessive amplification of these peaks and other nonlinearities, power amplifiers (PAs) need to “back off” from operating at maximum linear power, and instead...

2021-187 - Millimeter-Wave Class EF Power Amplifier with Concurrent Harmonic and Subharmonic Tuning

Market Opportunity Sensing and communication using the millimeter wave band is a promising new approach for applications like mm-wave 5G systems and radar. These systems generally utilize power amplifiers (PAs), the peak and power back-off efficiency of which is crucial for power and thermal management. While class E/F switching PA has emerged as a...

2021-188 - SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning

Market Opportunity In-memory computing (IMC) is a promising alternative to traditional digital machine learning algorithms due to its energy efficiency. Past IMC research used a digital-to-analog converter (DAC) to encode multi-bit input into pulse count, pulse width, or an analog voltage, which has limitations such as static power consumption and...

Published: 2/3/2026 Inventor(s): Mike Shuo-Wei Chen, Rezwan Rasul
Keywords(s):  

2022-075 - Time-Domain ADC with a SAR TDC

Market Opportunity The need for high-speed, medium-resolution analog-to-digital converters (ADCs) is rapidly growing due to the increasing demand for wideband communication integrated circuits. The traditional voltage-domain time- interleaved SAR time-to-digital converter (TDC) is an efficient option, but its single-channel sample rate is limited,...

2023-009 - Circuit Accelerator for Boolean Satisfiability

Hardware and software verification Logistics Autonomous systems Abstract USC researchers have designed a circuit arrangement to accelerate solving of the SAT algorithm. This two-part circuit uses a memory cell to represent values of a Boolean satisfiability expression and a constraints network that modifies the memory cell. The design builds...